Method for addressing a memory

ABSTRACT

A method for addressing a random access memory for writing data to the memory and reading data from the memory. The memory includes at least one bank, a plurality of rows and a plurality of columns. The manner for writing data to the memory and the manner for reading data from the memory are carried out according to a first or a second addressing type, wherein the addressing type for writing and reading is selected on the basis of parameters of the data and the processing which is to be carried out on the data. The data processing includes transposition of a data matrix, and the data are written to the memory with the aid of burst mode addressing, and the data are read from the memory with the aid of open-row addressing.

The present invention relates to a method for addressing a random accessmemory for writing data to the memory and reading data from the memory,in which the memory comprises at least two banks, a plurality of rowsand a plurality of columns.

European patent application EP-A-0 959 428 describes an image-processingdevice, in which a specific memory addressing method is used to write toand read from a memory. Video data comprising Y, C and K components witha data width of 32 bits are entered in parallel into the device and arerearranged into video data with Y, C and K components in series at eachsampling point with a data width of 10 bits. These data are written outin a horizontal direction as a burst into an SDRAM (synchronous dynamicrandom access memory) with a burst length of four. For each samplingpoint, exchange from the bank in the SDRAM is effected in such a waythat pixels adjacent to one another are always stored in differentbanks. In each bank, each component (Y, C, K) is given a consecutiveaddress (n, n+1, n+2). Through alternate switching of the banks duringmemory read-out, data can be read in burst mode in the horizontal orvertical direction, to be rearranged in the horizontal or verticaldirection. The described method therefore groups data associated withone pixel (10 bits Y, C and K data and two dummy bits), and stores thesein burst mode alternately in one bank and the other bank of a memory insuch a way that adjacent pixels are stored in different banks. Thisenables data associated with one pixel to be read out at high speed (inburst mode) in both the horizontal and vertical directions.

Due to the required multiplexing of the input signal (and demultiplexingof the read signal), a difference exists between the data speed of theinput signal and the data speed required for the memory. Furthermore,the described method requires only one type of addressing in order toaccess a memory (burst mode addressing).

It is currently obvious to prefer memories of the dynamic type (DRAM)over memories of the static type (SRAM) for all sorts of applications.The reason for this is that DRAM is available in larger sizes (aplurality of Mbits per chip) than SRAM, and DRAM is less expensive thanSRAM (by a factor of 100 per Mbit), since DRAM is used in PCs. Thedisadvantage of memories of the DRAM type is that high-speed access isrestricted to normal addressing schemes such as linear addressing. Theuse of random access in DRAM memories results in reduced performance.Furthermore, the dynamic nature of DRAM requires that each memory bit isperiodically refreshed, since data are otherwise lost. This refreshingof data in the memory requires additional control operations, since therefresh process interferes in most cases with the addressing schemeswhich are used.

The present invention is intended to provide a method for memoryaddressing and a dynamic memory with which a dynamic random accessmemory (DRAM) can be used in an efficient manner for high-speed readingand writing of data from the memory in a random sequence with no loss ofperformance. In addition, the present invention intends to produce amethod for refreshing a DRAM which has minimal impact on the high-speedrandom read-out from the DRAM.

According to the present invention, a method of the type defined in thepreamble is produced, in which the manner of writing data to the memoryand the manner of reading data from the memory are carried out accordingto a first or a second addressing type, and in which the addressing typefor writing and reading is selected on the basis of parameters of thedata and the processing which is to be carried out on the data.

The present method enables memories to be written to and read from in ahighly efficient and fast manner. The writing of data to and the readingof data from a memory can be optimised for a specific application bymaking maximum use of two different addressing methods. The applicationis characterised by the parameters of the data and the operation whichis to be carried out. The present method can be used in particular inapplications wherein the sequence of large data sets is manipulated,such as in image processing, video processing, radar, medicalapplications, etc.

In a further embodiment of the present invention, the method furthercomprises the steps of checking whether the memory is busy performing aread or write operation; if so, waiting until the read or writeoperation can be interrupted, row-by-row refresh of the memory andcontinuation of the interrupted read or write operation.

This produces a highly efficient method for refreshing the data storedin a memory without reducing the efficiency of the addressing, byminimising the required additional control operations (overhead). Therefresh is deferred as far as possible until the time when it does notinterfere with the primary process (the reading from or writing to thememory).

In one embodiment, the first addressing type may be burst modeaddressing with a burst length of Q memory spaces, comprising the stepsof the opening of a row of the memory and the addressing of Q memoryspaces in that row by selecting a bank and a start column. This isparticularly advantageous if a large amount of data needs to be madeavailable on consecutive spaces in the memory for a specificapplication. The burst length Q may, for example, be 4, 8, 16 orinfinity.

Furthermore, consecutive burst sequences may be addressed to differentbanks of the at least one bank, thereby ensuring high-speed access tothe memory.

In an advantageous embodiment, the burst length Q is greater than thelatency L1 which is required in order to open a row in the memory. Thisoffers optimal utilisation of the data read-out.

In a further embodiment, the method further comprises the steps of theclosing of a current row, the activation of a following row and theselection of a series of memory spaces at a time when the content ofmemory spaces of the current row is available at the output of thememory. Through these parallel addressing steps, less time is lost inaccessing specific memory spaces in the memory, thereby increasing theaverage speed for accessing the memory. The time is selected, forexample, in such a way that the first memory space of a following row isavailable immediately after the last memory space of the current row. Byusing a fixed burst length Q for a specific application, this is simpleto implement as the latencies of the different steps in the addressingare defined (are dependent on the memory configuration).

The second addressing type comprises open-row addressing, whichcomprises the steps of the opening of a combination of a bank and a rowand the accessing of a plurality of memory spaces in that row throughsequential selection of a plurality of columns. Once a row is open, noadditional latency is required in order to access further memory spacesin the same row. The efficiency of the memory can thus be increasedthrough appropriate use of this addressing type in a specificapplication.

The random access memory may be a memory which is selected from thegroup comprising dynamic memories (DRAM), synchronous dynamic memories(SDRAM), dynamic memories with double data rate (DDR-DRAM), and Rambusmemories (RDRAM).

In one embodiment, the data processing comprises transposition of a datamatrix. The data are written to the memory with the aid of burst modeaddressing, and the data are read from the memory with the aid ofopen-row addressing. This enables highly efficient transposition of thedata matrix.

In a further aspect, the present invention relates to an addressingdevice for a random access memory with at least one bank, a plurality ofrows and a plurality of columns, in which the addressing means arearranged to carry out the method according to the present invention. Theaddressing means may be implemented in separate hardware components, ormay be integrated into the memory itself.

In a still further aspect, the present invention relates to a dynamicrandom access memory comprising at least one bank, a plurality of rowsand a plurality of columns, further comprising a priority control whichis linked to a refresh control, and a memory control which is linked tothe refresh control, in which the priority control has at least an idlemode, a read/write mode and a read/write interrupt mode, the refreshcontrol being arranged for the periodic transmission of a refreshrequest to the priority control and the despatch of a refresh command tothe memory control if the priority control is set to idle mode orread/write interrupt mode, in which the priority control is set toread/write interrupt mode if the read/write operation can be interruptedin read/write mode following receipt of a refresh request.

This implementation of the refreshing of a dynamic memory is highlyeffective and makes it possible to ensure refreshing of a memory,whereby no data will be lost from the memory.

The present invention will now be explained with reference to a numberof embodiments and to the attached drawings, in which:

FIG. 1 shows a schematic illustration of a dynamic random access memoryin which the present invention can be applied;

FIG. 2 shows a timing schedule for controlling the memory according toan embodiment of the present invention;

FIG. 3 shows a sample sequence of a 32×32 pixel image;

FIG. 4 shows a sample sequence of the 32×32 pixel image in FIG. 3 afterhaving been stored in a memory according to the present method;

FIG. 5 shows a status diagram of a priority control in an embodiment ofthe present invention;

FIG. 6 shows a context diagram of the priority control in FIG. 5.

A dynamic random access memory (DRAM) 5, as shown schematically in FIG.1, generally comprises M banks 6, in which each bank comprises N rows 7,and each row has P memory spaces 8 (also referred to as columns). Eachmemory space can be addressed in a unique manner and may comprise oneword (this may be 8 bits or 16 bits, depending on the memory type). Thememory size of a DRAM 5 is therefore M×N×P words. Typical values areM=4, N=4096 and P=512.

Before a memory space in a specific bank m can be read from or writtento, the relevant row n 7 must be opened. The opening of a row 7 isachieved by an ‘activate’ command which selects a specific row addressand a bank 6. After a latency of L1 clock cycles (generally L1=2), a‘read’ command selects the column p 8 of that row 7. After a latency ofL2 clock cycles (generally L2=2), the memory space is available at theoutput of the memory 5. A ‘write’ command is correspondingly used towrite to a memory space. The reading of memory addresses can similarlybe understood below to refer correspondingly in each case to the writingof memory addresses.

If the following memory space is located in the same row 7, this row 7can be kept open. The ‘read’ command for a different memory space in thesame row can be given immediately following the preceding ‘read’command, and these data are then available at the output immediatelyafter the previous data.

If the following memory space is not located in the same row 7, thecurrent row 7 must first be closed with the aid of a ‘close’ command,which can be given simultaneously with the last ‘read’ command. Once thecurrent row 7 is closed, the following row 7 can be opened in the sameway as described above.

It is similarly possible to read consecutive memory spaces in the samerow 7 in burst mode. This generally means that the memory spaces p, p+1,. . . , p+Q−1 are read following a ‘read’ command in burst mode. Thelength of the burst (reading or writing) may be Q memory spaces, where Qis generally equal to 4, 8, 16 or infinity. FIG. 2 shows the timediagram for accessing two consecutive data bursts in two different rows7.

The above rule represents the command line CMD, which can comprisecommands (READ, READ in burst mode, CLOSE, or inactive). In the linesbelow, the signals which are used represent the selection of a row (R),a bank (B) and a column (C). The final line indicates whether specificmemory spaces are available at the output of the memory.

The advantage of reading and writing in burst mode is that the commandbus CMD and address buses R, B, C are available, for example, foropening a following row 7 in a different bank 6. The current row 7 canthen be closed at the same time as the ‘read’ command, and the followingrow 7 can already be activated during the current access to the burstdata. It is thereby in principle possible to obtain the following burstdata immediately after the current burst data. FIG. 2 shows, forexample, that the memory spaces D1 of bank 1 and column 1 are availableL2 cycles after the ‘read’ and ‘close’ command. The ‘activate’ commandfor the following row (R2) is given immediately after the ‘read’ and‘close’ command. Only later is the ‘read in burst mode’ command givenfor reading from the memory spaces D2 in bank 2 and column 2 in row 2.

In order to prevent data loss in dynamic memories 5, each row in thememory 5 must be refreshed once every T μsec. In practice, this meansthat a ‘read’ or ‘write’ command or a ‘refresh’ command must be given atan interval of T μsec. The ‘refresh’ command refreshes a row 7 in allbanks 6 simultaneously. The memory 5 remembers which row 7 was the lastto be refreshed and the following row 7 is selected after a following‘refresh’ command. The refreshing of a row 7 requires a latency of L3clock cycles, where L3 is generally equal to seven. The refreshing ofmemory spaces with the ‘refresh’ commands can interfere with theaddressing of the memory 5 in order to read or write data.

According to the present invention, memory spaces in a DRAM 5 arequickly accessible with two levels of freedom. The levels of freedomrelate to freedom in terms of column addressing, and freedom in terms ofrow addressing. Quickly accessible means that the access frequency isclose to one access of a memory space per clock cycle, even if memoryspaces are located in a plurality of rows.

The present method uses two types of addressing (both for reading fromand writing to the memory 5). The first type is burst mode addressing,as shown in FIG. 2. In this specific burst mode, a row 7 is closed atthe same time as the address of the first memory space is offered on thebank and column address bus (‘read and close’ command in the same clockcycle as the bank address and column address). The opening of a new row7 and the addressing of the following burst can take place while theremaining memory space of the current burst is accessed. Optimumaddressing takes place if the burst length Q is greater than or equal tothe latency L1 of the ‘activate’ command. In this case, the ‘read andclose’ command can in fact be given at such a time that the lastaccessing of a memory space of the current burst is immediately followedby the first accessing of a memory space of the following burst. Asshown in FIG. 2, the available memory spaces then precisely follow,whereby data can be read from or written to the memory 5 as efficientlyas possible.

The second type of addressing is open-row access. This makes use of thefact that, once a row is opened, memory spaces in the same row 7 can beread from or written to without loss of access time. If the number ofconsecutive accesses in a row is equal to the length of the row, theloss is minimal. If Pcon is the number of samples which areconsecutively read or written in a row, the following row must then beopened after Pcon clock cycles. Ppen is the number of clock cycles whichare additionally required to close the current row 7 and activate thefollowing row 7. The additionally required loss time (overhead) is thenPpen/Pcon. It therefore follows from this that the greater Pcon is, theshorter the additionally required loss time is. It is similarly possibleto address consecutive memory spaces during open-row access, in a mannercorresponding to burst mode addressing.

Highly efficient addressing can be achieved by using one or both ofthese types of addressing for writing data and then reading out datadepending on the data parameters and the required processing of the dataconcerned.

This will now be explained in more detail with reference to an examplerelating to high-speed transposition of an image. This is based on animage of 32×32 samples. In FIG. 3, the image is shown as 32×32 sampless1 . . . s1024. The image is written line by line (row order) to amemory 5, but must be read in column order. The row-order writeoperation is carried out with the aid of the burst mode addressingdescribed above, and the column-by-column read-out from the memory 5 iscarried out by means of open-row addressing. In this case, the DRAMmemory has 4096 rows, 512 columns, 4 banks and a burst length of 4.

An address of a memory space is denoted as (p, q, r), where p is the rownumber, q is the column number and r is the bank number. FIG. 4 showshow the samples of the image are stored in the memory 5 using thepresent method.

The first sample s1 is stored in memory space (1,1,1) and the followingthree samples s2, s3, s4 are written to the following memory spaces(1,2,1), (1,3,1) and (1,4,1) (burst length 4). During the writing of thefirst burst, the following row (1,:,2) can be opened, which is done byincrementing the bank number. This procedure is repeated for all 32samples in the first rule, whereby s17 again occurs in bank 1, but withan incremented row number (2,:,1).

The first sample s33 of the second line of the image is written in thesame row (1,5,1) as the first sample of the first line. The procedure isrepeated for the second line (and for the remaining 30 lines) as above.Once all 32×32 samples have been written, the situation illustrated inFIG. 4 occurs. It is now clear that the first four columns are locatedin the same row, i.e. (1,:,1). These can therefore be read efficientlycolumn-by-column with open-row addressing as described above. The secondfour columns are similarly present in the same row, i.e. (1,:,2), etc.,and can therefore also be read out in an efficient manner.

The required refreshing of the data in a DRAM 5 can often interfere withthe addressing (reading or writing) of the memory spaces, particularlyif data are read from or written to the memory 5 in a continuous manner.The reading and writing of memory spaces must, as far as possible, begiven priority, but sometimes a ‘refresh’ command needs to be givenpriority in order to prevent loss of data in the memory 5.

According to the present invention, use is therefore made of a prioritycontrol 10 (see also FIG. 6 which is discussed below), which has fivemodes, as shown in FIG. 5:

‘idle’ (11): this mode is the normal mode, to which the priority control10 always returns;

-   -   ‘refresh’ (12): this is the standard refresh mode, to which the        priority control 10 is set following a low-priority refresh        request;    -   ‘init’ (13): this is an initialisation mode, to which the        priority control 10 is set following activation of the memory        supply, and following a change of the DRAM mode;    -   ‘R/W controller’ (14): in this mode, memory spaces are read from        the memory 5 or are written to the memory 5. An R/W controller        mode is added for each addressing scheme;    -   ‘R/W interrupt’ (15): if a high-priority refresh request is        received during a read or write operation, the priority control        10 is set to this mode.

FIG. 5 shows not only the various modes, but also the transitionsbetween them. Thus, on completion of a refresh (mode 12), the end of theinitialisation (mode 13) and the end of a read or write operation (mode14) the priority control 10 will revert to idle mode 11. At the end of arefresh in the ‘R/W interrupt’ mode 15 of the priority control 10, thelatter will revert to the relevant ‘R/W control’ mode 14 to which thepriority control 10 was previously set.

In the ‘idle’ mode 11, a low-priority refresh request is always handledin ‘refresh’ mode 12. Requests of this type may be submitted early, butgenerally these requests are made only when necessary, since the memory5 requires a relatively large amount of power during a refresh.Low-priority refreshes never interfere with read and write operationsand generally require simple handling procedures. During a read or writeoperation of the memory 5 (‘R/W control’ mode 14), a low-priorityrefresh request is handled only if the latter does not interfere withany read or write operation. If it does interfere, the priority control10 waits for the first possible moment before switching to ‘R/Winterrupt’ mode. On completion of the high-priority refresh, thepriority control 10 reverts to the relevant ‘R/W control’ mode 14 inorder to complete the read or write operation. High-priority refreshrequests of this type therefore require special handling procedures.FIG. 6 shows the environment in-which the priority control 10 operates.The DRAM control 10 (which, inter alia, controls the addressing of thememory 5) communicates with a refresh control 17, which in turn isconnected to the priority control 10.

If the priority control 10 is set to ‘idle’ mode 11, as indicated by thestatus signal 22, the refresh control 17 generates control signals 18 toensure that one or more refresh cycles are carried out by the DRAMcontrol 16. The DRAM control 16 communicates the mode of the memory 5 tothe refresh control 17 by means of a refresh status signal 19.

The refresh control 17 generates a refresh request 20 for the prioritycontrol 10, which is set to ‘R/W control’ mode 14, i.e. there is a riskof data loss. As soon as the priority control 10 switches to ‘R/Winterrupt’ mode 15 (as indicated by the status signal 22), the refreshcontrol 17 in turn generates the control signals 18 for the DRAM control16. From the refresh mode signal 19, the refresh control 17 canascertain whether the memory is again free for read or write access.This mode forwards the refresh control 17 to the priority control 10 viathe memory mode signal 21, which can indicate that the memory 5 istherefore not available for other controls.

In one example, the refresh is described for a DRAM memory 5 whichrequires 4096 refresh cycles every 64 msec. The strategy for carryingout the refresh is that of distributed refresh. The refresh control 17generates control signals 18 with the aid of a counter (not shown) whichgenerates one pulse every 15.625 μsec. If no refresh has taken place inthe preceding 15.625 μsec and the priority control 10 is set to ‘idle’mode 11, the counter pulse will produce the control signals 18. If thepriority control 10 is set to ‘R/W control’ mode 14 when the counterpulse occurs, the refresh control 17 will first wait until the prioritycontrol switches to ‘R/W interrupt’ mode 15 before the control signals18 (forced refresh) are sent to the DRAM control 16. The refresh request18 may comprise a series of commands for the DRAM control 16, which arerequired in order to carry out one refresh cycle, for exampleimplemented in a state machine. This state machine can then similarly beused to indicate to the priority control 10 that the memory 5 is notfree for other controls.

The refresh strategy can of course be selected in a different way,whereby an optimum choice must be made between hardware requirements andthe number of forced refreshes that take place.

1-12. (Cancelled)
 13. A method for addressing a random access memory forwriting data to the memory and reading data from the memory, wherein thememory includes at least: one bank; a plurality of rows; and a pluralityof columns, wherein the manner of writing data to the memory and themanner of reading data from the memory are carried out according to oneof a first and a second addressing type, wherein the addressing type forwriting and reading is selected on the basis of parameters of the dataand the processing which is to be carried out on the data.
 14. Themethod according to claim 13, further including the steps of: checkingwhether the memory is busy performing a read or write operation; waitinguntil the read or write operation can be interrupted when the memory isbusy performing the read or write operation; refreshing the memoryrow-by-row; and continuing the interrupted read or write operation. 15.The method according to claim 14, wherein the first addressing type isburst mode addressing with a burst length of Q memory spaces, whereinperforming the burst mode addressing includes the steps of: opening arow of the memory; and addressing Q memory spaces in that row byselecting a bank and a start column.
 16. The method according to claim15, wherein consecutive burst sequences are addressed to different banksof the at least one bank.
 17. The method according to claim 16, whereinthe burst length Q is greater than a latency L1 required to open the rowin the memory.
 18. The method according to claim 16, further includingthe steps of: closing a current row; activating a following row; andselecting a series of memory spaces at a time when a content of memoryspaces of the current row is available at an output of the memory. 19.The method according to claim 17, further including the steps of:closing a current row; activating a following row; and selecting aseries of memory spaces at a time when a content of memory spaces of thecurrent row is available at an output of the memory.
 20. The methodaccording to claim 18, wherein the time is selected so that the firstmemory space of the following row is available immediately after thelast memory space of the current row.
 21. The method according to claim15, wherein the second addressing type includes open-row addressing,wherein performing open-row addressing comprises the steps of: opening acombination of a bank and a row; and accessing a plurality of memoryspaces in that row through sequential selection of a plurality ofcolumns.
 22. The method according to claim 13, wherein the random accessmemory is one of dynamic memories (DRAM), synchronous dynamic memories(SDRAM), dynamic memories with double data rate (DDR-DRAM), and Rambusmemories (RDRAM).
 23. The method according to claim 22, wherein the dataprocessing includes the steps of: transposing a data matrix; writing thedata to the memory with the aid of burst mode addressing; and readingthe data from the memory with the aid of open-row addressing.
 24. Anaddressing device for a random access memory, wherein the memorycomprises: at least one bank; a plurality of rows; and a plurality ofcolumns, wherein the addressing device is operative for selecting one ofa first and a second addressing type, wherein the addressing type forwriting and reading to the memory is selected on the basis of parametersof the data and the processing which is to be carried out on the data.25. The addressing device according to claim 24, wherein the addressingdevice is further operative for: checking whether the memory is busyperforming a read or write operation; waiting until the read or writeoperation can be interrupted when the memory is busy performing the reador write operation; refreshing the memory row-by-row; and continuing theinterrupted read or write operation.
 26. The addressing device accordingto claim 25, wherein the first addressing type is burst mode addressingwith a burst length of Q memory spaces, wherein performing the burstmode addressing includes the steps of: opening a row of the memory; andaddressing Q memory spaces in that row by selecting a bank and a startcolumn.
 27. The addressing device according to claim 26, whereinconsecutive burst sequences are addressed to different banks of the atleast one bank.
 28. The addressing device according to claim 27, whereinthe burst length Q is greater than a latency L1 required to open the rowin the memory.
 29. The addressing device according to claim 27, whereinthe addressing device is further operative for: closing a current row;activating a following row; and selecting a series of memory spaces at atime when a content of memory spaces of the current row is available atan output of the memory.
 30. The addressing device according to claim29, wherein the time is selected so that the first memory space of thefollowing row is available immediately after the last memory space ofthe current row.
 31. The addressing device according to claim 26,wherein the second addressing type comprises open-row addressing,wherein performing open-row addressing comprises the steps of: opening acombination of a bank and a row; and accessing a plurality of memoryspaces in that row through sequential selection of a plurality ofcolumns.
 32. A random access memory including: at least one bank; aplurality of rows; a plurality of columns; a priority control linked toa refresh control; and a memory control linked to the refresh control,wherein the priority control has at least: an idle mode; a read/writemode; and a read/write interrupt mode, wherein the refresh control isarranged for a periodic transmission of a refresh request to thepriority control and a dispatch of a refresh command to the memorycontrol if the priority control is set to one of the idle mode and theread/write interrupt mode, and wherein the priority control is set tothe read/write interrupt mode if a read/write operation is interruptedin the read/write mode following receipt of the refresh request.